253668.pdf
Intel 64 and IA-32 Volume 3A System Programming Guide


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CHAPTER 1 - Introduzione
1.1 PROCESSORS COVERED IN THIS MANUAL
1.3 Notational Convention.
1.3.1	Bit and Byte Order
1.3.2 Reserved Bits
1.3.3 Instruction Operands
1.3.4 Hexadecimal and Binary Numbers
1.3.5 Segmented Addressing
1.3.7 Exceptions
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CHAPTER 2 - SYSTEM ARCHITECTURE OVERVIEW - Introduzione
		(solo Real Mode e Protected Mode)
		(no IA-32 Extended 64 bit Mode (no IA-32e mode)
2.1 OVERVIEW OF THE SYSTEM-LEVEL ARCHITECTURE
		(No Figure 2-2)
2.1.1 Global and Local Descriptor Tables
2.1.2 System Segments, Segment Descriptors, and Gates
2.1.3 Task-State Segments and Task Gates
2.1.4 Interrupt and Exception Handling
2.1.5 Memory Management
2.1.6 System Registers
2.2 MODES OF OPERATION
		(solo Protected mode e Real Address Mode)
2.3 SYSTEM FLAGS AND FIELDS IN THE EFLAGS REGISTER 
		(solo prime 4 righe)
2.4 MEMORY-MANAGEMENT REGISTERS
2.4.1 Global Descriptor Table Register (GDTR)
2.4.2 Local Descriptor Table Register (LDTR)
2.4.3 IDTR Interrupt Descriptor Table Register
2.4.4 Task Register (TR)
2.5 CONTROL REGISTERS 
		(solo CR0, CR2, CR3)
2.7 SYSTEM INSTRUCTION SUMMARY
2.7.1 Loading and Storing System Registers
2.7.5 Controlling the Processor 
	(solo per approfondimento facoltativo)
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CHAPTER 3 - PROTECTED-MODE MEMORY MANAGEMENT
3.1 MEMORY MANAGEMENT OVERVIEW
3.2 USING SEGMENTS - Introduzione
3.2.1 Basic Flat Model
3.2.2 Protected Flat Model
3.2.3 Multi-Segment Model
3.2.5 Paging and Segmentation
3.3 PHYSICAL ADDRESS SPACE
3.4 LOGICAL AND LINEAR ADDRESSES
3.4.2 Segment Selectors
3.4.3 Segment Registers
3.4.5 Segment Descriptors (solo per approfondimento)
3.4.5.1 Code- and Data-Segment Descriptor Types 
		(solo per approfondimento)
3.5 SYSTEM DESCRIPTOR TYPES
3.5.1 Segment Descriptor Tables
		(solo prime 9 righe)

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CHAPTER 4 PAGING - Introduzione
4.1 PAGING MODES AND CONTROL BITS  
		(solo per approfondimento)
4.1.1 Three Paging Modes
		(solo 32-bit paging)
4.2 HIERARCHICAL PAGING STRUCTURES: AN OVERVIEW
		(solo page 4-7 e prime 8 righe page 4-8 (32-bit paging))
4.3 32-BIT PAGING
		(solo pages 4-9, 4-10, 4-11 e figure 4-2 e 4-3)
4.12 USING PAGING FOR VIRTUAL MEMORY
4.13 MAPPING SEGMENTS TO PAGES

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CHAPTER 5 PROTECTION - Introduzione
5.5 PRIVILEGE LEVELS 
		(solo page 5-9 e meta page 5-10 fino a 4 righe dopo la figura)
5.8 PRIVILEGE LEVEL CHECKING WHEN TRANSFERRING PROGRAM CONTROL BETWEEN CODE SEGMENTS (solo per approfondimento)
5.8.1 Direct Calls or Jumps to Code Segments (solo per approfondimento)
5.8.2 Gate Descriptors
5.8.3 Call Gates (solo per approfondimento)
5.8.4 Accessing a Code Segment Through a Call Gate (solo per approfondimento)
5.8.5 Stack Switching (importante figura 5-13)
5.8.6 Returning from a Called Procedure
5.9 PRIVILEGED INSTRUCTIONS
5.11 PAGE-LEVEL PROTECTION
5.12 COMBINING PAGE AND SEGMENT PROTECTION
		(NON USARE table 5-3)

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CHAPTER 6 INTERRUPT AND EXCEPTION HANDLING
6.1 INTERRUPT AND EXCEPTION OVERVIEW
6.2 EXCEPTION AND INTERRUPT VECTORS
6.3 SOURCES OF INTERRUPTS
6.3.1 External Interrupts
6.3.2 Maskable Hardware Interrupts
6.3.3 Software-Generated Interrupts
6.4 SOURCES OF EXCEPTIONS
6.4.1 Program-Error Exceptions
6.4.2 Software-Generated Exceptions
6.4.3 Machine-Check Exceptions (solo per approfondimento)
6.5 EXCEPTION CLASSIFICATIONS
6.6 PROGRAM OR TASK RESTART (solo per approfondimento)
6.7 NONMASKABLE INTERRUPT (NMI) (solo per approfondimento)
6.8 ENABLING AND DISABLING INTERRUPTS
6.8.1 Masking Maskable Hardware Interrupts  (solo per approfondimento)
6.8.3 Masking Exceptions and Interrupts When Switching Stacks  (solo per approfondimento)
6.9 PRIORITY AMONG SIMULTANEOUS EXCEPTIONS AND INTERRUPTS  (solo per approfondimento)
6.10 INTERRUPT DESCRIPTOR TABLE (IDT)
		(page 6-12 e fino a prime 16 righe di page 6-13, piu' figure 6-1)
6.11 IDT DESCRIPTORS
6.12 EXCEPTION AND INTERRUPT HANDLING
6.12.1 Exception- or Interrupt-Handler Procedures
6.12.1.1 Protection of Exception- and Interrupt-Handler Procedures (solo per approfondimento)
6.12.2 Interrupt Tasks
6.13 ERROR CODE (solo per approfondimento)

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CHAPTER 7 TASK MANAGEMENT
7.1 TASK MANAGEMENT OVERVIEW
7.1.1 Task Structure
7.1.2 Task State
7.1.3 Executing a Task
7.2 TASK MANAGEMENT DATA STRUCTURES
7.2.1 Task-State Segment (TSS)
7.2.2 TSS Descriptor (solo per approfondimento)
7.2.4 Task Register
7.2.5 Task-Gate Descriptor (solo per approfondimento)
7.3 TASK SWITCHING
		(solo punti 1, 8, 11, 12, 13, e fino a fine pagina 7-14)
7.4 TASK LINKING